1. Field of the Invention
The present invention relates to telecommunications apparatus and methods. More particularly, the present invention relates to ATM switch arbitration apparatus and methods for limiting data bursts in the switch, and thereby permitting simplified output port electronics.
2. State of the Art
Asynchronous transfer mode (ATM) is perhaps the fastest growing segment of the telecommunications backbone. The purpose of ATM is to provide a high-speed, low-delay multiplexing and switching network which supports all types of user traffic, including voice, data, and video. ATM data is transported in fixed-length "cells" which are fifty-three bytes in length, including a five byte header and a forty-eight byte data packet. The header includes virtual path and virtual circuit identifiers (VPI and VCI) which are used by the ATM network in relaying the traffic through switches of the network and to its customer premise equipment (CPE) destinations.
Many different ATM switches are known in the art. Generally, the switches have a plurality of input ports with input queue buffers, a plurality of output ports with associated queue buffers, and a source traffic control system which includes a switch fabric or bus mechanism and a switch controller which controls the transfer of data among the ports. A well-accepted source traffic control system for accomplishing switching is known in the art as CELLBUS.RTM. (a registered trademark of the assignee hereof TranSwitch, Corp.) which is described in detail in the previously incorporated patent application Ser. Nos. 08/960,499 and 08/961,932. The CELLBUS.RTM. mechanism is an asynchronous data transfer and source traffic control system which includes a bus master (switch controller) and a plurality of bus users (ports) coupled to a bidirectional data bus. The bus master preferably provides two clock signals to each bus user, a system clock and a frame clock. The frame clock designates the start of a frame. A frame format preferably includes fifteen or sixteen system clock cycles, the first of which is designated the request field and the last of which includes a grant field. One or more other cycles may be assigned control and/or routing information and the remainder of the cycles comprise a data field of fixed length. During the request field, any number of bus users may request access which is received by the bus master. During the grant field, the bus master grants access to a selected bus user for the entire data portion of the next frame. Which user is granted access to the next frame is determined according to an arbitration algorithm in the bus master which may be unknown to the bus users.
In the CELLBUS.RTM. system, as well as in other source traffic control systems, arbitration for access to the shared bus in order to accomplish switching is based on knowledge of the sender's identity. As described in the previously incorporated patent applications, simple arbitration algorithms, such as round-robin, may be used, resulting in the utilization of simple arbiters of low complexity and cost. While round-robin and other simple arbitration algorithms generally reduce the cost and complexity of the arbiters, additional cost is generated in the input buffers, as each input buffer must be long enough to allow for the time the port waits for bus access. More complex arbitration systems are known which reduce input buffer costs. However, regardless of the complexity of the arbitration system, no mechanisms are presently available in ATM switches which employ shared buses to reduce output port buffers. Indeed, in the systems of the art, it is not uncommon that long bursts from a single input port which are intended for a single output port are broken only by short bursts to other ports. This bursty traffic necessitates a worst case design of output port electronics at both a hardware and software level, as each port must be capable of accepting data at the speed of the bus for an indeterminate amount of time. The result is an expensive design with large high speed memories (buffers).